The present invention relates to a method of manufacturing a semiconductor device having copper interconnects. The present invention has particular applicability to manufacturing high density semiconductor devices with submicron design features.
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 microns and under, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional methodology.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally made of monocrystalline silicon, and multiple dielectric and conductive layers formed thereon. In a conventional semiconductor device 100 illustrated in FIG. 1, substrate 1 is provided with field oxide 2 for isolating an active region including source/drain regions 3, and a gate electrode 4, typically of doped polysilicon, above the semiconductor substrate with gate oxide 5 therebetween. Interlayer dielectric layer 6, typically silicon dioxide, is then deposited thereover and openings formed using conventional photolithographic and etching techniques. The openings are filled with conductive material to establish electrical contact between subsequently deposited conductive layer 8 and source/drain regions 3 through contacts 7, and to transistor gate electrode 49. Dielectric layer 9, typically silicon dioxide, is deposited on conductive layer 8, and another conductive layer 10, typically aluminum or an aluminum-base alloy, formed on dielectric layer 9 and electrically connected to conductive layer 8 through vias 11.
With continued reference to FIG. 1, conductive layer 10 is the uppermost conductive layer and, hence, constitutes the wire bonding layer. Dielectric layer 12, also typically silicon dioxide, is deposited, and a protective dielectric scratch resistant topside layer 13 is deposited thereon. Protective dielectric layer 13 typically includes a nitride layer, such as silicon nitride (Si3N4). Alternatively, protective dielectric layer 13 may include a dual topcoat comprising a nitride layer on an oxide layer. The protective dielectric layer 13 provides scratch protection to the semiconductor device 100 and protection against moisture and impurity contamination during subsequent processing. After deposition of protective dielectric layer 13, conventional photolithographic etching techniques are employed to form an opening to expose wire bonding layer 10 for external connection via bonding pad 14 and electrically conductive wires 15 or an external connection electrode (not shown).
Although only two conductive layers 8 and 10 are depicted in FIG. 1 for illustrative convenience, conventional semiconductor devices may include more than two conductive layers, e.g., five conductive metal layers, depending on design requirements. Also in the interest of illustrative convenience, FIG. 1 does not illustrate any particular type of plug or barrier layer technology. However, such technology is conventional and, therefore, the details of such features are not set forth herein.
As device features continue to shrink in size, the interconnects, such as contacts 7 and vias 11 enable the semiconductor device 100 to offer more packing density, higher speeds and more flexibility in circuit design. Various metals, such as aluminum and aluminum-base alloys, have typically been used to form the interconnects. More recently, copper and copper-base alloys have also been used to form the electrical interconnects. In such cases, the copper is typically deposited via a single electroplating process. That is, a single plating solution employing one type of plating chemistry is supplied to an electroplating chamber where the electroplating proceeds to fill the openings that will form the interconnects. The plating solution is typically recirculated to process in excess of 1000 wafers before being discarded.
The filling of small features via electroplating depends heavily on the plating solution chemistry. For example, some plating solutions are designed for bottom-enhanced filling. That is, the plating solution includes additives designed to fill the bottom portion of an opening more quickly than other portions of the opening. Unfortunately, these-bottom enhanced chemistries lead to preferential filling over certain features. For example, FIG. 2 illustrates a dielectric layer 22 with openings 24a-e and 26 formed on a semiconductor substrate 20. Electroplating semiconductor device 200 with a bottom-enhanced plating chemistry may leave excessive plating materials 28 above features located close together, such as openings 24a-e, as illustrated in FIG. 2. Excessive plating materials may also form over openings such as opening 26. In addition, in openings with high aspect ratios, such as openings 24a-e, the sidewalls of the openings may close in before the bottom portion has completely filled, thereby leaving a void in the opening. The void may cause problems with electrical continuity and may further add to excessive plating materials being deposited above the openings.
Other plating chemistries are designed to conformally fill various features. That is, the plating solution fills all portions of the openings equally. As a result, a conformally deposited layer 29 typically leaves an uneven topography across the wafer, as illustrated in FIG. 3.
In both cases, i.e., bottom-enhanced filling and conformal filling, the non-uniform, non-planar result of the electroplating poses a challenge to subsequent processes, such as chemical-mechanical polishing (CMP). For example, performing CMP on semiconductor device 200 of FIG. 2 to remove the excessive plating materials 28 may result in significant erosion of the dielectric layer 22. Additionally, performing a CMP on semiconductor device 200 of FIG. 3 may result in xe2x80x9cdishing,xe2x80x9d of the openings. That is, the CMP may remove some conductive material in the openings, such as opening 26, below the level of the upper surface of the dielectric layer 22, as illustrated by the dashed lines in FIG. 3. These problems associated with performing CMP may adversely affect the performance of the interconnects.
There exists a need for methodology for forming copper interconnects that facilitates subsequent planarization and improves interconnect performance.
These and other needs are met by the present invention, where two or more plating chemistries are employed to fill openings for forming copper interconnects. The resulting topography is more planar and facilitates subsequent planarization.
Additional advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages and features of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of forming an interconnect in a semiconductor device. The method includes forming an opening in a dielectric layer and depositing copper to fill a portion of the opening using a first plating process. The first plating process employs a first plating solution designed for non-conformal filling of the opening. The method also includes depositing copper to fill the opening using a second plating process. The second plating process employs a second plating solution designed for conformally filling the opening. The method further includes planarizing the semiconductor device so that the copper-filled opening is substantially coplanar with an upper surface of the dielectric layer.
According to another aspect of the invention, a method of manufacturing a semiconductor device includes forming a plurality of levels of dielectric layers and conductive layers on a semiconductor substrate. The method also includes forming an opening in at least one of the dielectric layers, supplying a first plating solution to an electroplating chamber and depositing copper to fill a portion of the opening. The first plating solution is designed for non-conformal filling of the opening. The method further includes terminating the supply of the first plating solution after the portion is deposited, supplying a second plating solution to the electroplating chamber and depositing copper to fill the opening. The second plating solution is designed for conformal filling of the opening.
Other advantages and features of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive.